Semiconductor integrated circuits are fabricated using photolithographic techniques on thin semiconductor disks commonly referred to as “wafers.” Regarding a semiconductor wafer, the side of the wafer where a majority of circuits are formed is commonly referred to as the “device side” or “front side” or “top side” and the opposite side is commonly referred to as the “backside” or “bottom side.” When forming the integrated circuits on the semiconductor wafer, a space between them is required for separating the circuits into individual units. Those spaces are termed “scribe lines” or “scribe streets” or “saw streets.” The photolithographic techniques performed during fabrication of the integrated circuits on the semiconductor wafer use photolithographic patterns formed on glass or other transparent plates which are commonly referred to as “photomasks.” In the photolithographic processing, a photoresist layer is formed over the semiconductor wafer. This layer is formed of photosensitive material. The photoresist layer is used to control the specific wafer areas that are subjected to subsequent steps such as etch, implant, or oxide formation for example. A photomask is then positioned and light is used to transfer the pattern of the photomask onto the photoresist. The exposed photoresist (depending on the chemical composition, the photoresist can be a positive or negative resist) is then chemically developed and areas of the photoresist are removed or are not removed depending on the pattern of the photomask. The manufacture of the various components in current complex integrated circuit manufacture often requires more than a dozen of these photomasks be used in a specific order, each containing a pattern that is transferred to the photoresist and the pattern is then used to process the wafer. The spatial alignment of each of the photomasks to the semiconductor wafer is critical to the successful creation of the components of the integrated circuit.
To facilitate the visual alignment of the photomasks to the semiconductor wafer, features are formed in the photomasks and also on the device side of the wafers that are called “alignment marks.” The wafer alignment marks are formed during processing of the wafer and may be formed of a metal that was patterned in a prior processing step, e.g. tantalum, tungsten, titanium, platinum, chromium, gold, or the like, or by etching trenches or shapes into the silicon. As the continuing processing can destroy, damage or obscure prior alignment marks, additional alignment marks can sometimes be made at later processing steps to ensure alignment is possible for subsequent processing.
Traditionally, integrated circuits have been built on a single side, the device side, of the semiconductor wafer. Alignment marks are also formed on the device side of the wafer, commonly several times as the processing of the wafer can render an existing alignment mark unusable for the following process steps. In recent modern integrated circuits, particularly those including Micro Electrical and Mechanical System (MEMS) devices, integrated circuit devices are sometimes created with structures or components on opposing sides of the wafer, the device side and the backside. A common backside component for MEMS devices is a cavity on the backside of the wafer. The cavity can extend to the devices formed on the device side of the wafer. For example, a backside etch can be used to create a lens opening corresponding to a MEMS device or to a photocell. The backside processing has created a need for an alignment camera on the chuck side of the processing tools as well as the normal position on the device side of the wafer. This backside processing requirement arises because the alignment marks, previously formed on the device side of the wafer, are now positioned facing the tool chuck, or downwards. A camera or microscope located under the wafer chuck enables the use of the device side alignment marks to be used to align the wafer to the photomask. This is called “front-to-back” alignment or “F2B” alignment. In typical F2B alignment, the system compares an alignment mark on the device side of a wafer to a photomask positioned above the opposing backside of the wafer. In some systems, an image superposition is performed and displayed during alignment so that the reference marks and the alignment marks can be visually compared and alignment can be performed until the relative spatial positions are correct.
Differentiating between the alignment marks on the wafer and the marks on the photomask, the alignment marks on the photomasks are commonly referred to as “reference marks” and the marks on the wafers are commonly referred to as “alignment marks.” Using the alignment marks and the reference marks together, the photomasks and the semiconductor wafers are visually aligned during the processing of the wafer.
Alignment and reference marks are used by both automated optical recognition systems as well as by human operators. Automated and manual alignment systems are used and some systems begin with an initial visual manual alignment and then use automatic alignment to complete the visual alignment process. Alternatively, a coarse alignment can be performed automatically with the human operator completing the visual alignment. Alignment cameras or microscopes are used that have various stages of magnification, where the lower power magnification provides a wider field of view and the higher power magnifications provide finer resolution and facilitate more precise alignment. Magnification can be from 1× to 10× or more depending on the stage of the semiconductor processing. Displays such as computer monitors are used to assist the visual alignment process.
FIG. 1A depicts in a prior art illustration the various components involved in the device side alignment. A device side alignment camera 110 focuses “down” toward the photomask 120. The wafer 130, which is positioned with the device side “up” towards the photomask, is affixed to the wafer chuck 140, typically with a vacuum. The backside alignment camera 150 is pointed upwards as shown. In the conventional device side processing, the backside alignment camera 150 is typically not used.
Initially the photomask 120 is positioned in the processing tool in a known location. The wafer chuck 140 is moved to a loading position (not illustrated) where a wafer 130 is placed on the wafer chuck with the device side up. A vacuum source (not shown) is employed to hold the wafer to the chuck. The wafer chuck 140 then moves to an initial rough alignment position beneath the photo mask 120. The device side alignment camera or microscope 110 is used to look down through the photomask while the operator or alternatively, an automatic system, moves the wafer chuck 140 until the wafer alignment marks are visually centered with the photomask reference marks. In some arrangements, the initial alignment is performed manually and subsequent alignments can be performed automatically. The wafers can be visually aligned in at least 2 locations to the photomask to ensure proper alignment.
FIG. 1B depicts in a prior art illustration the previous components of FIG. 1A now configured for F2B alignment. A device side alignment camera 110 focuses down toward the photomask 120. The wafer 130, which is positioned with the backside oriented “up” as shown in FIG. 1B, so that a photoresist can be patterned to enable a subsequent etch or another semiconductor manufacturing operation to be performed on the backside, is affixed to the wafer chuck 140, typically with a vacuum. The backside alignment camera 150, mounted under the wafer chuck 140, is pointed upwards as illustrated and can view the wafer thru slots 142a, 142b in the wafer chuck.
Initially the photomask 120 is positioned in the processing tool in a known location and the photomask reference marks are located using the device side alignment camera 110. The position and image of the reference marks are stored so they can be transferred to a display (not shown) for use with the backside alignment camera 150. The wafer chuck 140 is moved to a loading position (not illustrated) where a wafer 130 is placed on the wafer chuck with the backside up and device side down as illustrated. Note that the alignment marks formed on the device side are now viewable by the backside alignment camera 150 thru slots 142a and 142b. A vacuum source (not shown) is employed to hold the wafer to the chuck. The wafer chuck 140 then moves to an initial rough alignment position beneath the photo mask 120. At that point, an image of the photomask reference mark can be displayed on the backside alignment camera display. The backside alignment camera 150 focuses up through a slot 142 and superimposes its image on the display, along with the photomask reference mark image.
In operation, the operator or a machine automated system can move the wafer chuck 140 until the wafer alignment marks are visually centered with the photomask reference marks. The initial F2B alignment is typically done manually and subsequent alignments can be performed automatically. In alternative approaches the alignment can be performed entirely manually, or can be performed by an automated visual system such as a machine visual system, or the manual steps can complete the alignment. Using slot 142b, a second F2B alignment can be performed to ensure alignment. Additional alignment marks and reference marks can be used to further ensure proper alignment.
FIGS. 2A-C depict in a prior art illustration sample photomask reference marks and wafer alignment marks. Wafer 200 in FIG. 2A has scribe line alignment mark 230 as shown in the enlargement 210 in FIG. 2C. Photomask 202 in FIG. 2B has scribe line reference mark 220, 222 as shown in the enlargement 210 in FIG. 2C. In this example a “box/cross” alignment mark set is situated in a scribe line and can be used for aligning a wafer to a photomask. In this example, small box shapes 222 are set within a larger box shape 220 to serve as the photomask reference marks. A “cross” figure, depicted as 230 is formed on the wafer as the alignment mark. In one example for a conventional semiconductor process, the general dimension of the outer box of the reference mark 220 is typically 80 um×80 um, although other sizes could be used. This limits the minimum scribe street width 212 to greater than 80 um.
FIGS. 3A-3C depict in a second prior art illustration another sample photomask reference mark and the corresponding wafer alignment marks used in a conventional alignment process. In this example, wafer 300 in FIG. 3A has an alignment mark 330 formed in the scribe line as shown in the enlargement 310 in FIG. 3C. Photomask 302 in FIG. 3B has a corresponding reference mark 320 as shown in the enlargement 310 in FIG. 3C. In this example, a “circle/diamond” alignment mark set is situated in a scribe line and used for alignment of a wafer to a photomask. In this example illustrative implementation, the round dot 320 serves as the photomask reference mark. A “diamond” figure, depicted as 330, is formed on the wafer as the alignment mark. The general dimension of the diameter of the dot 320 in one example is 80 um. This limits the minimum scribe street width 312 to greater than 80 um.
On the semiconductor wafer, only the areas that are formed into circuits are eligible as finished devices for revenue generation, the other areas are used for items, such as scribe lines, process test structures, alignment marks and other test and visual inspection items, and these areas of the wafer all become part of the overhead in the manufacture of the semiconductor wafer. Because many of the processing steps in semiconductor manufacturing affect the entire wafer, some of the steps have costs that are somewhat independent of the number of devices that are provided per wafer. By increasing the number of devices per wafer, then, the per unit costs can be reduced. Accordingly, there is continual incentive to minimize the integrated circuit size, thus increasing the number of integrated circuit devices produced per each wafer processed, and thereby decreasing the unit cost. This also leads to continual incentive to reduce the non-device areas. Integrated circuits have continued to shrink as the minimum feature sizes of the semiconductor processes used for manufacture have shrunk. For this reason, a scribe line that is held to a minimum dimension of 80 ums or greater for example, in order to contain a corresponding alignment mark of a similar minimum dimension, will consume a larger and larger percentage of the wafer area as the device sizes shrink. The constant scribe line width increases costs and reduces the number of completed devices obtained per wafer.
Alignment marks with dimensions of about 80 um are already at a near minimum size that can be viewed at about 1× magnification, which is customary in the F2B alignment process utilizing backside alignment cameras currently used. A continuing need thus exists for solutions that enable the shrinking of the scribe lines to less than 60 um while maintaining alignment marks on the photomasks and on the wafers that are sufficiently large to be compatible with the existing photomask alignment infrastructure at 1× magnification. The solutions should be compatible with existing and future alignment equipment, and should be useful without the need to modify process tools already in production.